1. Field of the Invention
The present invention relates to a shift register and a shift register unit, and more particularly to a shift register and a shift register unit used for diminishing clock coupling effect.
2. Description of the Prior Art
Conventional liquid crystal display (LCD) utilizes a set of driving circuits for controlling gray signal outputs of a plurality of pixel units located in a LCD panel. The driving circuits further include a gate driver electrically connected with transverse scan lines (or gate lines) in turn each for outputting a gate pulse signal to each corresponding pixel unit, and a source driver electrically connected with longitudinal data lines (or source lines) each for transmitting a data signal to each corresponding pixel unit 20 separately. Each of the intersections between the transverse scan lines and longitudinal data lines is electrically connected with two terminals of an active component (such as a transistor having a gate and a source) corresponding to the pixel unit. At the same time when the gate driver outputs gate pulse signals in turn via the scan lines to turn on the transistor of each pixel unit, the source driver outputs corresponding data signals via the data lines to charge a capacitor of each pixel unit to reach a required voltage level so as to display various gray levels.
To lower chip expense of the gate driver, the conventional Thin-Film Transistor LCD (TFT-LCD) panel based on such as a Low Temperature Poly-Silicon (LTPS) process technique adopts an integrated gate driver module design, by way of relocating a shift register from the existing gate driver chip to the glass substrate, to constitute cascaded multi-stage shift register modules as implementing “Gate on Array (GOA)”. This functions as same as the shift register did in the original gate driver. Because the LTPS-based panel mostly adopts Poly-Silicon transistors, the Poly-Silicon transistors have a mobility of over two-hundred multiple than that of amorphous-Si transistors. However, for the same reason as reducing the panel cost, the a-Si process with a very low mobility also realize such a circuit design on its glass substrate, gradually.
Presently, a shift register design adopted by the most conventional integrated gate driver modules is disposed with a pull-down module or the likes to prevent the gate pulse signal output of the shift register from distortions invoked by pull up of other signals. Such a pull-down module is mostly driven by a clock signal (CK) or an inverted clock signal (XCK). Please refer to FIG. 1A, which is illustrated with a schematic circuitry diagram of the Nth stage shift register 210 as disclosed in U.S. Pat. No. 7,310,402 B2. In the Nth stage shift register 210, all of a pull-up transistor Q2 and two pull-down modules 1 and 2 employ a first clock signal (CK1). Although a prefect waveform of an ideal first clock signal (CK1-ideal) is introduced in FIG. 1B, the first clock signal (CK1) is inevitably involved with a coupling effect of a capacitor inhering between both of the drain and gate of the pull-up transistor Q2 under an actual operation and therefore transforms into a waveform of a real first clock signal (CK1-real), as depicted in FIG. 1C., with a curved edge “E1” representing a slower rising velocity. This would cause periodic occurrences of a plurality of upward spikes “B1” on waveform output (Out) of the gate pulse signal as depicted in FIG. 1D. Simultaneously, with involvement of driving the pull-down modules 1 and 2 in delays by the first clock signal (CK1), a signal level of either an output node (P8) or an input node (P2) of a pull-up module containing the pull-up transistor of Q2 also would not be timely pulled down and therefore provides a poor pull-down performance. Besides, an ideal second clock signal (CK2-ideal) as depicted in FIG. 1E employed by the pull down module 2 also is transformed into a real second clock signal (CK2-real) as depicted in FIG. 1F, based on the same coupling effect as occurring in the first clock signal (CK1), with the curved edge “E1” representing a slower rising velocity. This causes periodic occurrences of a plurality of downward spikes “B2” on the waveform output (Out) of the gate pulse signal as depicted in FIG. 1D.
Hence, it is a significant topic of how to deal with such a problem.